FIG. 10 is a circuit diagram of a three-phase inverter. The three-phase inverter circuit shown in FIG. 10 includes an upper arm; a lower arm; a U-terminal, a V-terminal, and a W-terminal connected to the respective connection points of the upper and lower arms; a P-terminal connected to the high-potential side of the upper arm; an N-terminal connected to the low-potential side of the lower arm; semiconductor switching devices such as IGBT's constituting the upper and lower arms; and free-wheeling diodes (hereinafter referred to as “FWD's”) connected in opposite parallel to the respective IGBT's.
FIG. 11(a) is the top plan view of a conventional semiconductor apparatus. FIG. 11(b) is the cross sectional view along the single-dotted chain line X-X in FIG. 11(a). FIG. 11(c) is the bottom plan view of the conventional semiconductor apparatus showing the base including fins formed thereon.
Referring now to these drawings, conventional semiconductor apparatus 600 is a power semiconductor module that constitutes the three-phase inverter circuit shown in FIG. 10 thereon.
In the following descriptions, Si-IGBT chip 54 is a silicon insulated-gate bipolar transistor chip and SiC-Di chip 55 is an FWD chip made of a silicon carbide Schottky barrier diode (SBD).
The three-phase inverter circuit includes the U-phase, V-phase and W-phase. Since the chip arrangements in these phases are the same, the chip arrangement in the U-phase is described exemplary.
In semiconductor apparatus 600, electrically conductive film 52c of insulated substrate 52 is fixed onto base 51. Insulated substrate 52 includes electrically conductive patterns 52a and 53a formed thereon. Base 51 includes fins 51a formed thereon. The collector of Si-IGBT chip 54 on the upper arm and the cathode of SiC-Di chip 55 on the upper arm are fixed onto electrically conductive pattern 52a. The collector of Si-IGBT chip 54 on the lower arm and the cathode of SiC-Di chip 55 on the lower arm are fixed onto electrically conductive pattern 53a. 
The emitter of Si-IGBT chip 54 on the upper arm and the cathode of SiC-Di chip 55 on the upper arm are connected to each other with wiring bar 56. The emitter of Si-IGBT chip 54 on the lower arm and the cathode of SiC-Di chip 55 on the lower arm are connected to N-terminal bar 59. Electrically conductive pattern 52a is connected to P-terminal bar 58. The cathode of SiC-Di chip 55 on the upper arm and electrically conductive pattern 53a are connected to each other with wiring bar 57. Wiring bar 57 is connected to U-terminal bar 57a. 
Since the chip arrangements in the V- and W-phases are the same with the chip arrangement in the U-phase, the duplicated descriptions on the chip arrangements in the V- and W-phases are omitted for the sake of simplicity.
U-terminal bar 57a, V-terminal bar 57b, and W-terminal bar 57c are connected to a not-shown load. P-terminal bar 58 and N-terminal bar 59 are connected to a not-shown power supply. The connection points of these terminals are exposed from a not-shown resin case.
On each of three insulated substrates 52, two Si-IGBT chips 54 and two SiC-Di chips 55 constituting the upper and lower arms are mounted and arranged in adjacent to each other. By arranging Si-IGBT chips 54 and SiC-Di chips 55 constituting the upper and lower arms collectively on the same insulated substrate 52, the heat values generated by operating Si-IGBT chips 54 and SiC-Di chips 55 on insulated substrates 52 are set to be the same.
Therefore, the generated heat values on insulated substrates 52 are equalized, fins 51a constituting base 51 are arranged with an equal spacing. Fin 51a is a plate-shaped tooth (rectangular parallelepiped). The spaces between fins 51a under insulated substrates 52 are equal. The spaces between fins 51a are set to be narrow for dissipating the heat generated by chips 54 and 55 effectively.
FIG. 12(a) is a cross sectional view describing the way of cooling semiconductor apparatus 600. FIG. 12(b) is a bottom plan view describing the way of cooling semiconductor apparatus 600.
Referring now to these drawings, cover 60 is set on base 51 including fins formed thereon. Although not illustrated, cover 60 includes an inlet for making coolant 61 flow in and an outlet for making coolant 61 flow out. Coolant 61 made to flow in from the inlet passes through the spaces between fins 51a and flows to the outlet. Coolant 61 flows through the close spaces between fins 51a. For making coolant 61 pass through the spaces between fins 51a, it is necessary to pressurize coolant 61. The pressure necessary to make coolant 61 pass through the spaces between fins 51a (the different pressure between at the inlet and at the outlet) is referred to as the “pressure loss.” Usually, coolant 61 is circulated by a not-shown pump.
FIG. 13(a) is a cross sectional view describing the thermal interference caused between the chips in semiconductor apparatus 600. FIG. 13(b) is the cross sectional view along the single-dotted chain line X-X in FIG. 13(a) describing the thermal interference occurred between the chips in semiconductor apparatus 600. FIG. 13(c) is the cross sectional view along the single-dotted chain line Y-Y in FIG. 13(a) describing the thermal interference occurred between the chips in semiconductor apparatus 600.
When the three-phase inverter circuit operates, thermal interference occurs between Si-IGBT chip 54 and SiC-Di chip 55.
Now thermal interference 71 will be described below with reference to FIG. 13(b).
When Si-IGBT chip 54 on the U-phase upper arm is operating but SiC-Di chip 55 on the U-phase lower arm is not, Si-IGBT chip 54 generates heat and the heat generated is transferred from electrically conductive pattern 52a to adjacent electrically conductive pattern 53a through insulator substrate 52b. The transferred heat makes the temperature, which is low, of chip 55 fixed to electrically conductive pattern 53a rise. When SiC-Di chip 55 on the U-phase lower arm is operating but Si-IGBT chip 54 on the U-phase upper arm is not, the Si-IGBT chip 54 temperature, which is low, is raised.
Now, thermal interference 72 will be described below with reference to FIG. 13(c).
Because SiC-Di chip 55 on the U-phase upper arm is not operating, while Si-IGBT chip 54 on the U-phase upper arm is operating, Si-IGBT chip 54 generates heat and the generated heat makes the adjacent SiC-Di chip 55 temperature, which is low, rise via electrically conductive pattern 52a. When SiC-Di chip 55 on the U-phase upper arm is operating but Si-IGBT chip 54 on the U-phase upper arm is not, the Si-IGBT chip 54 temperature, which is low, is raised.
Because thermal interference 71 occurs via insulator substrate 52b and thermal interference 72 via electrically conductive pattern 52a, thermal interference 72 is larger than thermal interference 71. Thermal interference 71a caused through base 51 including fins 51a formed thereon is small, therefore the heat generated is dissipated almost to coolant 61 via fins 51a. The distances M1 and M2 between chips 54 and 56, and the distance M3 between insulated substrates 52 including an electrically conductive pattern formed thereof are several mm.
Thermal interference 72 between Si-IGBT chip 54 and SiC-Di chip 55 occurs through electrically conductive pattern 52a exhibiting a high thermal conductivity and near to the heat sources. Thermal interference 71 between Si-IGBT chip 54 and SiC-Di chip 55 occurs through insulator substrate 52b near to the heat sources and far from the coolant. Therefore, thermal interference 72 and thermal interference 71 caused in conventional semiconductor apparatus 600 are large.
FIG. 14 is a top plan view describing the heat exchanges between the chips via terminal bars in conventional semiconductor apparatus 600.
Thermal interference 65 occurs through wiring bar 56 connecting the Si-IGBT chip 54 emitter and the SiC-Di chip 55 anode on the upper arm. Thermal interference 66 occurs through N-terminal bar 59 connecting the Si-IGBT chip 54 emitter and the SiC-Di chip 55 anode on the lower arm. Thermal interference 67 occurs through wiring bar 57 connecting the Si-IGBT chip 54 anode on the upper arm and electrically conductive pattern 53a on the lower arm.
The distance between the connection point of wiring bar 56 and the Si-IGBT chip 54 emitter on the upper arm and the connection point of wiring bar 56 and the SiC-Di chip 55 anode on the upper arm is designated by N1. The distance between the connection point of N-terminal bar 59 and the Si-IGBT chip 54 emitter on the lower arm and the connection point of N-terminal bar 59 and the SiC-Di chip 55 anode on the lower arm is designated by N2. The distance between the connection point of wiring bar 57 and the Si-IGBT chip 55 anode on the upper arm and the connection point of wiring bar 57 and electrically conductive pattern 53a is designated by N3. Since the distances N1, N2, and N3 are short, from 1 cm to several cm, thermal interference 65, thermal interference 66, and thermal interference 67 are large.
The operable temperature of SiC-Di chip 55 is 250° C. However, the operable temperature of Si-IGBT chip 54 is 175° C. If SiC-Di chip 55 is operated at 250° C., the Si-IGBT chip 54 temperature will exceed 175° C. to the higher side, causing thermal destruction of Si-IGBT chip 54.
Because the operable temperature of the semiconductor apparatus is determined by the operable temperature of Si-IGBT chip 54, it is necessary to restrict the operating temperature of SiC-Di chip 55 to be 175° C. or lower.
Japanese Unexamined Patent Application Publication No. 2009-272482 (also referred to herein as “Patent Document 1”), discloses a semiconductor apparatus that includes a first laminate structure, a second laminate, and a connection section connecting the first and second laminates electrically to each other. The first laminate structure includes a first heatsink, a first isolation layer, a first electrically conductive layer, and a first semiconductor device (silicon IGBT). The second laminate structure includes a second heatsink, a second isolation layer, a second electrically conductive layer, and a second semiconductor device (SiC diode). The semiconductor apparatus separates the first and second laminate structures from each other such that the first and second laminate structures are thermally insulated from each other.
In the semiconductor apparatus disclosed in the Patent document 1, the Si-IGBT chips constituting an upper arm are aligned to form an upper arm Si-IGBT chip group. The SiC-Di chips constituting the upper arm are aligned to form an upper arm SiC-Di chip group. The Si-IGBT chips constituting a lower arm are aligned to form a lower arm Si-IGBT chip group. The SiC-Di chips constituting the lower arm are aligned to form a lower arm SiC-Di chip group. The upper arm Si-IGBT chip group and the upper arm SiC-Di chip group are arranged alternately. The lower arm Si-IGBT chip group and the lower arm SiC-Di chip group are arranged alternately. The coolant flows through the Si-IGBT chip group and, then, through the SiC-Di chip group. In other words, the semiconductor apparatus disclosed in the Patent Document 1 includes two coolant paths for cooling the chips constituting the upper arm and for cooling the chips constituting the lower arm. The coolant path is long.
Since the operable temperature of Si-IGBT chip 54 is 175° C. as described above, it is impossible to operate SiC-Di chip 55 at the operable temperature thereof, that is 250° C. Since Si-IGBT chip 54 and SiC-Di chip 55 are arranged in close proximity to each other, the thermal interference between Si-IGBT chip 54 and SiC-Di chip 55 is large. Therefore, for improving the cooling efficiency, it is necessary to set the distance between fins 51a to be short (to arrange fins 51a more closely). However, the close arrangement of fins 51a increases the pressure loss of coolant 61, further increasing the size of the pump for circulating the coolant. As a result, the manufacturing costs of the entire inverter system soar.
In the Patent Document 1, the cooling structure in which Si-IGBT chip is positioned, is the same with the cooling structure in which SiC-Di chip is positioned. Moreover, the Si-IGBT chip group and the SiC-Di chip group are arranged in adjacent to each other. Therefore, it is impossible to raise the operating temperature of the SiC-Di chip to the operable temperature thereof. Although a thermal insulation structure is formed between the Si-IGBT chip group and the SiC-Di chip group, thermal interference occurs between the Si-IGBT chip and the SiC-Di chip because of a connecting wire that is not shown.
Two coolant paths are formed in the cooling structure. Since the coolant paths are complicated and long, the coolant pressure loss is large. Therefore, the pump for circulating the coolant is large inevitably. As a result, the manufacturing costs of the entire inverter system soar.
In view of the foregoing, it would be desirable to obviate or lessen the problems described above. It would be also desirable to provide a semiconductor apparatus, including a Si semiconductor device, a SiC semiconductor device, and a base including fins formed thereon, that facilitates operating the semiconductor devices at the respective operating temperatures and reducing the pressure loss of the coolant.